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HCF40105B
FIFO REGISTER
s
s s s
s s
s s s
s s
INDEPENDENT ASYNCHRONOUS INPUTS AND OUTPUTS 3-STATE OUTPUTS EXPANDABLE IN EITHER DIRECTION STATUS INDICATORS ON INPUT AND OUTPUT RESET CAPABILITY STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
ORDER CODES
PACKAGE DIP TUBE HCF40105BEY T&R
DESCRIPTION HCF40105B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP packages. HCF40105B is a low power first-in-first-out (FIFO) "elastic" storage register that can store 164-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. "1" signifies that the position's data is filled and "0" denotes a vacancy in that PIN CONNECTION
position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripples through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data is removed from the bottom of the data stack (the output and), all data entered later will automatically propagate (ripple) toward the output.
October 2002
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HCF40105B
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2 3 15 14 4, 5, 6, 7 13, 12, 11, 10 9 8 16 SYMBOL 3-STATE CONTROL DIR SI SO DOR D0 to D3 Q0 to Q3 MR VSS VDD NAME AND FUNCTION 3-State Control Data-In Ready Shift In Shift Out Data-Out Ready Input Buffers Output Buffers Master Reset Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLE
CONTROL INPUTS PRESET MODE CLR H H H H L APE H H H L X SPE H H L X X CI/CE H L X X X Synchronous Inhibit Counter Count Down Preset on Next Positive Clock Transition Preset Asynchronously Clear to Maximum Count ACTION
Asynchronous
X : Don't Care Clock connected to Clock input Synchronous Operation : changes occur on negative to positive clock transitions.
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HCF40105B
LOGIC DIAGRAM
TIMING CHART
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HCF40105B
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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HCF40105B
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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HCF40105B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol tPHL Parameter Propagation Delay Time Shift-out or Reset to Data out Ready Propagation Delay Time Shift-in to Data-in Ready VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 185 90 65 160 65 45 140 60 40 100 50 40 2 1 0.7 100 50 40 1.5 3 4 100 40 30 180 80 50 Max. 370 180 130 320 130 90 280 120 80 200 100 80 4 2 1.4 200 100 80 3 6 8 ns Unit
tPHL
ns
tPZH tPLZ Propagation Delay Time 3-State Control to Data-out tPHZ tPLZ Propagation Delay Time 3-State Control to data-out tPLH Ripple-trough Delay Input to Output
ns
ns
s
tTHL tTLH Transition Time
ns
fI
Shift-in or Shift-out Rate
MHz
tWH
Shift-in Pulse Width
tWL
Shift-out Pulse Width
200 80 60 360 160 100
ns
ns 15 15 15 15 15 15 15 5 5
tr
Shift-in or Shift-out Rise Time Shift-in Fall Time
s
tf
s
tf
Shift-out Fall Time
s
tsetup
Data Setup Time
thold
Data Hold Time
0 0 0 350 150 120
ns 175 75 60 260 100 70
ns 520 120 140
tWL
Data-in Ready Pulse Width
ns
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HCF40105B
Test Condition Symbol tWL Parameter Data-out Ready Pulse Width Master Reset Pulse Width VDD (V) 5 10 15 5 10 15 Min.
Value (*) Typ. 220 90 665 100 45 30 Max. 440 180 130
Unit
ns
tWH
200 90 60
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
TYPICAL APPLICATION: EXPANSION, 4 BIT-WIDE-BY-16 N-BITS LONG.
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HCF40105B
TYPICAL APPLICATION: EXPANSION, 8 BITS-WIDE-BY-16 N-BITS LONG.
APPLICATION INFORMATION LOADING DATA Data can be entered whenever the DATA-IN READY (DIR) flag is high by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily until the data has been transferred to the second location. The flag will remain low when all 16-word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. UNLOADING DATA As soon as the first word has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data is available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a "1" marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on)
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while the SHIFT-OUT is at logic "0". This level change causes the first word to be shifted out (unloaded) immediately and the data to be lost. CASCADING HCF40105B can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4-bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in parallel, if expanding is done in both directions. 3-STATE OUTPUTS In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. MASTER RESET A high on the MASTER RESET (MR) sets all the control logic marker bits to "0". DOR goes low and DIR goes high. The contents of the data register do not change, only declared invalid, and will be superseded when the first word is loaded.
HCF40105B
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
SWITCH Open VDD VSS
WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
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HCF40105B
WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
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HCF40105B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF40105B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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